1. Field of the Invention
The present invention relates to a semiconductor process, and more particularly, to a process of manufacturing a deep trench capacitor of a DRAM device.
2. Description of the Prior Art
Trench-capacitor DRAM devices are known in the art. A trench-storage capacitor typically consists of a very-high-aspect-ratio contact-style hole pattern etched into the substrate, a thin storage-node dielectric insulator, a doped low-pressure chemical vapor deposition (LPCVD) polysilicon fill, and buried-plate diffusion in the substrate. The doped LPCVD silicon fill and the buried plate serve as the electrodes of the capacitor. A dielectric isolation collar in the upper region of the trench prevents leakage of the signal charge from the storage-node diffusion to the buried-plate diffusion of the capacitor.
In general, the prior art method for fabricating a trench capacitor of a DRAM device may include several major manufacture phases as follows:
Phase 1: deep trench etching.
Phase 2: buried plate and capacitor dielectric (or node dielectric) forming.
Phase 3: first polysilicon deep trench fill and first recess etching.
Phase 4: collar oxide forming.
Phase 5: second polysilicon deposition and second recess etching.
Phase 6: third polysilicon deposition and third recess etching.
Phase 7: shallow trench isolation (hereinafter referred to as “STI”) forming.
Please refer to FIG. 1 to FIG. 3. FIG. 1 is a schematic diagram illustrating an enlarged portion of a typical deep trench capacitor in cross-sectional view along line NN of FIG. 2. FIG. 2 shows the normal layout of the active areas (hereinafter referred to as “AA”) and deep trench capacitors (hereinafter also referred to as “DT”) 11 and 12 without DT-AA misalignment after accomplishing STI process, wherein perspective buried strap out diffusion 16 is shown. FIG. 3 depicts misaligned AA and DT layout after accomplishing STI process. Referring initially to FIG. 1, two adjacent deep trench capacitors (DT) 11 and 12 are fabricated in a semiconductor substrate 10, wherein each of which is comprised of a buried plate 13, node dielectric 14, poly stack storage node (Poly1/Poly2/Poly3). As known to those skilled in the art, the buried plate 13 acts as a first electrode of the deep trench capacitor, and the poly stack storage node (Poly1/Poly2/Poly3), which is electrically isolated from the buried plate 13 by the node dielectric 14, acts as a second electrode of the deep trench capacitor. Typically, the second polysilicon layer (Poly2) of the poly stack storage node (Poly1/Poly2/Poly3) is electrically from the surrounding substrate 10 by a so-called collar oxide 15. The deep trench capacitors 11 and 12 are electrically connected to respective access transistors (not shown), which are formed on the active areas 26, via the buried strap out diffusions 16. The deep trench capacitor 11 is electrically isolated from the deep trench capacitor 12 by the STI 20.
As the size of a memory cell shrinks, the chip area available for a single memory cell becomes very small. This causes reduction in capacitor area on a single chip and therefore leads to problems such as inadequate capacitance and large electrode resistance. In FIG. 1, two essential parameters are defined: X and L, wherein the parameter “X” stands for the maximum distance in the overlapping region between AA and DT in the x-direction, and the parameter “L” stands for the maximum distance of the DT in the x-direction subtracts the parameter “X”. In other words, the maximum width of the DT in the x-direction is the combination of the parameters “X” and “L”. It is often desired that to minimize the electrode resistance, the parameter “L” is kept as small as possible, while the parameter “X” is kept as large as possible. Larger “X” means longer AA region, and smaller “L” means narrower STI between two adjacent deep trench capacitors. Referring to FIG. 3, unfortunately, small “L” often leads to M-DT misalignment when defining AA and STI areas, and therefore causes capacitor charge leakage via diffusion region 17 as shown in dash line circle. When AA-DT misalignment occurs, the conductive diffusion region 17 is formed in the area between two adjacent deep trench capacitors 11 and 12, in which a STI is supposed to embedded therein for isolating the two adjacent deep trench capacitors 11 and 12.
Please refer to FIG. 4 and FIG. 5. FIG. 4 and FIG. 5 are schematic cross-sectional diagrams showing several intermediate steps of forming a prior art deep trench capacitor, which are relative to the present invention. As shown in FIG. 4, a substrate 10 having a pad oxide layer 26 and a pad nitride layer 28 thereon is provided. After deep trench etching, an N+ buried plate 13 and a node dielectric layer 14 are sequentially formed in the deep trench. A first polysilicon deposition and recess process is then carried out to form a first poly layer (Poly1) at the bottom of the deep trench. A collar oxide layer 15 is formed on sidewall of the deep trench above Poly1. A second polysilicon deposition and recess process is then carried out to form a second poly layer (Poly2) atopPoly1. As shown in FIG. 5, the collar oxide layer 15 that is not covered by Poly 2 is stripped off to expose the sidewall of the deep trench. Subsequently, a third polysilicon deposition and recess process is carried out to form a third poly layer (Poly3) atopPoly2. Dopants of the heavily doped Poly2 diffuse out through Poly3 to the surrounding substrate 10 to form an annular shaped buried strap out diffusion 16. Finally, a conventional STI process is performed to isolate the two adjacent deep trench capacitors, thereby forming the structure as set forth in FIG. 1.